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Honored Contributor
Honored ContributorAltsynRAM : 1 clock cycle Read/Write performance
Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_ForumHonored Contributor
Honored ContributorI guess the available options on the RAM block depends on the FPGA family, and you may not be able to remove the input registers on some families.
128 bytes isn't so much, you should be able to make your memory with registers instead of ALTSYNCRAM blocs, and in that case you can have it without registered inputs or outputs.
