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Honored ContributorAltsynRAM : 1 clock cycle Read/Write performance
Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_ForumHonored Contributor
Honored ContributorI disable output port registers, but address input port is registered. So, I need 2 clocks in a read cycle. In the first clock, the addres is registered and the data appears on the second clock.
