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Honored Contributor
Honored ContributorAltsynRAM : 1 clock cycle Read/Write performance
Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_ForumHonored Contributor
Honored ContributorSomething seems off. There are no asynchronous RAMs(MLABs are, but they're treates synchronously), but there is also nothing that requires two registers. You register the address, and the data comes out combinatorially later. There is no need for a second clock.
