AltsynRAM : 1 clock cycle Read/Write performance

I guess it's semantics, but if you drew the memory access as a schematic, there is only one register along the path, so that is generally referred to as one clock cycle of latency. You're basically saying you need the access in less than one clock cycle so it's completely out by the next clock cycle, or an asynchronous read. What device and what speed is the clock? If the clock is slow enough, then you could read on the falling edge of the clock, so it's available a half cycle earlier.