Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Hi Nicole,

I'm glad that your issue has been resolved.

We will try to improve the IP file name to avoid this issue in future.

Currently we cannot set the IP file name shorter automatically.

Manually edit the IP file name is possible.

Regards,

Adzim

Hi Adzim,

The width error seems to be fixed in the Quartus 25.1 version.

I do however still get the inclusion error. I have tried regenerating the IP, cleaning the project and regenerating again, but the error persists. The included file does exist.

Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_300_4hwut5y_emif_0_lpddr4_emif_io96b_lpddr4_300_ljjag6i.sv(17): cannot open include file emif_io96b_interface.svh

Kind regards,

Nicole

Hi Nicole,

I don't think you need to change in all files.

Make the change in the top IP file should be okay.

Try to regenerate the IP file again and make the change in the path that I have provided.

Regards,

Adzim

Hi,

The issue can be replicated if the EMIF IP is used VHDL code.

There is a parameter where the axi4_wuser width is determined.

If it does not use the NoC, the width is set to 64 for axi4_wuser.

The parameter can be found in the EMIF IP file path *_emif_io96b_lpddr4_0\emif_io96b_lpddr4_200\synth\*_emif_io96b_lpddr4_0_emif_io96b_lpddr4_200_*.sv.

localparam PORT_AXI_USER_WIDTH = 64,

localparam PORT_AXI_NOC_USER_WIDTH = 32,

localparam PORT_AXI_S0_USER_WIDTH = PHY_USE_NOC_INTF ? PORT_AXI_NOC_USER_WIDTH : PORT_AXI_USER_WIDTH,

Change the PORT_AXI_USER_WIDTH = 64 to 32 can resolve this error message.

Can you try to change the port width to 32 and check the compilation again?

Regards,

Adzim

We had similar problems - if we have checked Compile to VHDL (in Platform Designer/generate HDL). if ve have checked Compile to Verilog, problem gone away.

I have attached my project below for reference if it will help. My project only has the Agilex5 HPS IP, HPS EMIF IP, and FPGA EMIF IP. Both LPDDR4s are the same. HPS EMIF IP compiles successfully but the FPGA EMIF IP leaves me with the error (s0_axi4_wuser) shown above.

Hi Nicole,

Thank you for your feedback.

I will try to replicate the issue again with the file that you have shared.

Regards,

Adzim

Hi Nicole,

I cannot replicate the issue at my end. Can you share a small design that replicate this issue?

I can see a warning message that may sound related, but no error messages reported.

Warning(24541): Verilog HDL warning at as_emif_io96b_hps_0_emif_io96b_hps_200_e2lhgoi_emif_0_lpddr4.v(230): actual bit length 32 differs from formal bit length 64 for port "s1_axi4_ruser"

Regards,

Adzim

Any resolution to this issue? I am also running into this issue on 24.3.1. However, for me it is with the EMIF IP (Not for HPS) variant. The EMIF for HPS worked fine for me, however, I am using it as 1x32. The EMIF IP for FPGA DDR is also configured the same 1x32 but I am running into the issue above.

Both DDR (HPS and FPGA) are identical. Both configured as 1x32 for LPDDR4. HPS EMIF IP compiles fine, EMIF IP for FPGA DDR fails to compile with the same error mentioned above. I try to inspect the source where the error is originating however it appears to be two 32-bit wide ports connecting so I'm not sure where the 64-bit is coming from.

I also never had any issues with prior versions of Quartus. Please advise.

Hi Tiwari,

The issue has not been resolved. I need to use the 2x16 architecture.

The 1x32 also stopped working after regenerating the HDL. I get the following error for it too:
Error(17821): Netlist error at emif_bank2a_fpga.vhd(175): port 's0_axi4_wuser' of width 64 cannot connect to actual of width 32

The s0_axi4_wuser port is of width 32 in the mentioned .vhd file.

Please assist with this issue.

Kind regards,

Nicole