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Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Good day, I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the o...
Fpga Devkit
MM-ATH's avatar
MM-ATH
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

We had similar problems - if we have checked Compile to VHDL (in Platform Designer/generate HDL). if ve have checked Compile to Verilog, problem gone away.