Occasional Contributor
Regular ContributorHi,
The issue can be replicated if the EMIF IP is used VHDL code.
There is a parameter where the axi4_wuser width is determined.
If it does not use the NoC, the width is set to 64 for axi4_wuser.
The parameter can be found in the EMIF IP file path *_emif_io96b_lpddr4_0\emif_io96b_lpddr4_200\synth\*_emif_io96b_lpddr4_0_emif_io96b_lpddr4_200_*.sv.
localparam PORT_AXI_USER_WIDTH = 64,
localparam PORT_AXI_NOC_USER_WIDTH = 32,
localparam PORT_AXI_S0_USER_WIDTH = PHY_USE_NOC_INTF ? PORT_AXI_NOC_USER_WIDTH : PORT_AXI_USER_WIDTH,
Change the PORT_AXI_USER_WIDTH = 64 to 32 can resolve this error message.
Can you try to change the port width to 32 and check the compilation again?
Regards,
Adzim
Occasional ContributorHi Adzim,
Thank you for the update. Will an IP core update be made?
My one design works, but another gives a file inclusion error:
Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4_emif_io96b_cal_200_hpbproa.sv(17): cannot open include file cal_io96b_interface.svh
Kind regards,
Nicole
