Forum Discussion

Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Good day, I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the o...
Fpga Devkit
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi Nicole,


I cannot replicate the issue at my end. Can you share a small design that replicate this issue?


I can see a warning message that may sound related, but no error messages reported.

Warning(24541): Verilog HDL warning at as_emif_io96b_hps_0_emif_io96b_hps_200_e2lhgoi_emif_0_lpddr4.v(230): actual bit length 32 differs from formal bit length 64 for port "s1_axi4_ruser"


Regards,

Adzim


Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Hi Adzim,

Due to confidentiality, I can unfortunately not share my current design, but I had a similar issue (with 1x32) with a development kit. Here are those files. The full project is too large to share (let me know if I can email it). I have attached the top level and hps .qsys files.

We make use of VHDL. The warning you get is definitely related to the error that I get.

Kind regards,

Nicole