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Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Good day, I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the o...
Fpga Devkit
mfiorenza's avatar
mfiorenza
Icon for New Contributor rankNew Contributor
11 months ago

I have attached my project below for reference if it will help. My project only has the Agilex5 HPS IP, HPS EMIF IP, and FPGA EMIF IP. Both LPDDR4s are the same. HPS EMIF IP compiles successfully but the FPGA EMIF IP leaves me with the error (s0_axi4_wuser) shown above.