Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Any resolution to this issue? I am also running into this issue on 24.3.1. However, for me it is with the EMIF IP (Not for HPS) variant. The EMIF for HPS worked fine for me, however, I am using it as 1x32. The EMIF IP for FPGA DDR is also configured the same 1x32 but I am running into the issue above.

Both DDR (HPS and FPGA) are identical. Both configured as 1x32 for LPDDR4. HPS EMIF IP compiles fine, EMIF IP for FPGA DDR fails to compile with the same error mentioned above. I try to inspect the source where the error is originating however it appears to be two 32-bit wide ports connecting so I'm not sure where the 64-bit is coming from.

I also never had any issues with prior versions of Quartus. Please advise.