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Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Good day, I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the o...
Fpga Devkit
Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Hi Tiwari,

The issue has not been resolved. I need to use the 2x16 architecture.

The 1x32 also stopped working after regenerating the HDL. I get the following error for it too:
Error(17821): Netlist error at emif_bank2a_fpga.vhd(175): port 's0_axi4_wuser' of width 64 cannot connect to actual of width 32

The s0_axi4_wuser port is of width 32 in the mentioned .vhd file.

Please assist with this issue.

Kind regards,

Nicole