Two Master RAM Access

There is nothing wrong in the messages displayed by the IDE. What did you expect?

i think that message appears cause the HDL is accessing the DDR-RAM

heres a pic of my SOPC and of the Blockdiagram

reg  myState;          
reg  Data;
reg done;
reg counter;
assign Data = {8'hAF};     
     
always@(posedge CLK50)
begin
       if(!done)
       begin
       controllFIXED <= 0;
       controllWriteBase <= 32'h02000000;
        controllWriteLenght <= 32'h4;
        userBufferInput<= Data;
        if(myState == 0)
            begin
            controllGO<= 1;
            end
        else
            begin
            controllGO<= 0;
           end
        myState <= myState +1;
       if(!userBufferFull)
            begin
           userWriteBuffertoTheMaster<=1;
           end
        else
            begin 
            userWriteBuffertoTheMaster<=0;
           end
        if (controllDONE)
            begin
           myState <= 0;
           counter <= counter +1;
           end
        if (counter >= 2000)
        done <= 1;
        end
end

I'm not familiar with the template and how it works, but you should connect a Signaltap probe to the ports on your HDL to check if it isn't writing continuously. If it is, it will prevent the CPU from working properly.

I forgot to mention... you should give reset values for all your registers. If you don't your component can start in a strange state at power up.

mhh not that easy with that signaltap to get my signals -.-

I'm not sure I understand everything you are doing in your code. If mystate is 0 at the time that the counter reaches 2000, controllGO will stay at 1 forever.

oh ur right

So your HDL is overwriting the startup code, which isn't good... Is you application also located on the DDR?

hmm i thought i can access cause of that Master Modul with both Componentens, the HDL over the Master Modul and the NIOS II CPU.... mhh thought SoPC-Builder generates an Aribitation for both ... mhhh