Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

So your HDL is overwriting the startup code, which isn't good... Is you application also located on the DDR?

The best way to do it would be to have your software allocate a memory block and give its address to your HDL through a register (you'll need an Avalon slave interface for that).