SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

Hi,

In Agilex 7 M-Series Evaluation Kit clock tree, the 390.625 MHz SyncE (Synchronous Ethernet) recovered/reference clock is distributed through the Si5395/Si5391 clock generators and is used to generate clocks for the DDR5, HBM, and FPGA control/SDM interfaces.

My understanding is that a recovered SyncE clock is primarily intended for Ethernet frequency synchronization. Therefore, I am trying to understand the design rationale behind using it as the master reference for non-Ethernet interfaces on the board.

Could someone please clarify:

Why is the SyncE clock chosen as the primary reference for generating DDR5, HBM, and FPGA control interface clocks?

What are the advantages of using the SyncE reference instead of a dedicated crystal oscillator or another fixed-frequency reference?

Is this done to maintain frequency synchronization across the entire system, or are there other design considerations such as clock quality, jitter performance, or timing alignment?

Is this approach recommended only for the evaluation board, or is it also the recommended clocking architecture for custom Agilex M-Series designs?

Any explanation or reference to the relevant Intel documentation would be greatly appreciated.

Thank you.