Two Master RAM Access

heres a pic of my SOPC and of the Blockdiagram

reg  myState;          
reg  Data;
reg done;
reg counter;
assign Data = {8'hAF};     
     
always@(posedge CLK50)
begin
       if(!done)
       begin
       controllFIXED <= 0;
       controllWriteBase <= 32'h02000000;
        controllWriteLenght <= 32'h4;
        userBufferInput<= Data;
        if(myState == 0)
            begin
            controllGO<= 1;
            end
        else
            begin
            controllGO<= 0;
           end
        myState <= myState +1;
       if(!userBufferFull)
            begin
           userWriteBuffertoTheMaster<=1;
           end
        else
            begin 
            userWriteBuffertoTheMaster<=0;
           end
        if (controllDONE)
            begin
           myState <= 0;
           counter <= counter +1;
           end
        if (counter >= 2000)
        done <= 1;
        end
end