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Altera_Forum
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16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I'm not familiar with the template and how it works, but you should connect a Signaltap probe to the ports on your HDL to check if it isn't writing continuously. If it is, it will prevent the CPU from working properly.

Another reason could be that you are overwriting the reset or exceptions vectors in the DDR, making the CPU crash.