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Altera_Forum
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16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

mhh not that easy with that signaltap to get my signals -.-

i ll try the reset conditions

but what i don t understand is that it is blocked by my HDL cause after 2000 Writes it shouldn t access the ddr anymore -.-