Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

There is nothing wrong in the messages displayed by the IDE. What did you expect?

If your application isn't running, you can check first if it comes from your HDL or not. Something you can try is to recompile everything with your module disabled, and then see if it runs. If it is your component that freezes the system, it could be a good idea to use signaltap probes on its ports to see what it is doing.

Did you properly constrain your project and does it meet all timing requirements?