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Altera_Forum
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16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

oh ur right

i really should set ControllGo to 0 then...

u mean of my NIOS II ? the reset Vector is set to DDR-RAM and the exception to the On-Chip Memory