Slow Runtime Performance in FIL Implementation on DE2-115 Using Ethernet

Dear Technical Support Team,

I am currently working on an FPGA-in-the-Loop (FIL) implementation using the DE2-115 FPGA development board with MATLAB/Simulink.

My objective is to implement a complete PMSM drive system in FIL, which includes:

• A three-phase PWM inverter model
• A Permanent Magnet Synchronous Machine (PMSM) model

The system is developed in Simulink, converted to HDL, and deployed to the DE2-115 board using HDL Verifier.

The FIL setup is functioning correctly, and communication with the FPGA board through Ethernet is established successfully. The FPGA bitstream is generated and loaded without issues. However, during FIL simulation I observe that the runtime execution is very slow compared to the expected performance, and the simulation progresses significantly slower than real time.

I would like to ask whether this behavior is expected when implementing a full electrical drive system inside the FIL environment.

From reviewing several publications, it appears that many implementations only place a portion of the drive system in the FPGA. For example:

* Bogdan Fabiański, “FPGA Emulator of Switched Reluctance Motor in a FIL Structure,” Poznan University of Technology Academic Journals, Electrical Engineering, No. 87, 2016.

* Ahmet Gundogdu, Resat Celikel, Beşir Dandil, and F. Ata, “FPGA-in-the-loop implementation of direct torque control for induction motor,” Automatika, 2021, DOI: 10.1080/00051144.2021.1934365.

In these works, only specific parts of the system (such as the motor model or control algorithm) are implemented on the FPGA, while the remaining components remain in the simulation environment.

Therefore, I would appreciate your guidance on the following points:

1. Is it recommended to implement the entire drive system (inverter and machine model) inside the FIL for the DE2-115 platform?

2. Are there known performance limitations when using Ethernet-based FIL communication for relatively large models?

3. Is there a recommended partitioning strategy between the FPGA and Simulink for electric drive simulations?

If necessary, I can provide the model configuration, HDL Workflow Advisor settings, or additional implementation details.

Thank you for your support.

Kind regards,

Ahmed Sayed Soliman