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Ahmed_Sayed's avatar
Ahmed_Sayed
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7 days ago

Slow Runtime Performance in FIL Implementation on DE2-115 Using Ethernet

Dear Technical Support Team, I am currently working on an FPGA-in-the-Loop (FIL) implementation using the DE2-115 FPGA development board with MATLAB/Simulink. My objective is to implement a complet...
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paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
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4 hours ago

Hello Ahmed Sayed,

 

Thanks for submitting the query.

After going through the issue description, the question should be either raised to MATLAB/Terasic, not to Altera. I believe we won't be able to answer this.

Please reach out to MATLAB/TERASIC to get more detailed support on this matter.

 

Regards,

Pavee