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Altera_Forum's avatar
Altera_Forum
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16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

i think that message appears cause the HDL is accessing the DDR-RAM

that is also the exception Vector of the NIOS II

i think thats why i can t upload it

my question is what i have to do that i can access the RAM with 2 Masters

i want that one Master (the HDL one) writes about 185000 x 24 Bit Data on the DDR-RAM

after that the master should free the DDR ... dunno how that works

and the NIOS II SoftCore should read from the DDR-RAM the 185000 x 24 Bit Data

edit:

The Adress of the DDR-RAM is 0x02000000