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Altera_Forum
Honored Contributor
Honored ContributorTwo Master RAM Access
Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_ForumHonored Contributor
Honored Contributorhmm i thought i can access cause of that Master Modul with both Componentens, the HDL over the Master Modul and the NIOS II CPU.... mhh thought SoPC-Builder generates an Aribitation for both ... mhhh
