Occasional ContributorTiming violation when route emac from HPS to FPGA in quartus prime standard 18.1
Hi,
I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also.
I refer to the examples from here https://rocketboards.org/foswiki/Projects/CycloneVRGMIIExampleDesign
which uses RGMII interface for PHY.
I followed the important notes stated there:
1. use an ini file which has contents "b2t_enable_hps_emac_internal_clock_arcs = on" to enable the internal timing path from HPS clock mux.
2. I removed the content cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces.sdc
There is timing violation after compilation and fitting.
The violation is from cv_soc_rgmii_5csxfc6:soc_0|cv_soc_rgmii_5csxfc6_hps_0:hps_0|cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces:fpga_interfaces|peripheral_emac0~internal_clock
to phy_rgmii_rgmii_txd[0]. I.e. from the data clock (TX_SRC_CLK_125) to output clock (TX_CLK_OUT_125) of RGMII interface.
The timing constraint in soc_system_timing_sdc file related to those two clocks are as follows:
create_clock -name TX_SRC_CLK_125 -period "125 MHz" [get_keepers {soc_0|hps_0|fpga_interfaces|peripheral_emac0~internal_clock}] -add
create_generated_clock -name TX_CLK_OUT_125 \
-source [get_pins {ddio_out_1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel}] \
-master_clock TX_SRC_CLK_125 [get_ports phy_rgmii_rgmii_tx_clk] -add
#**************************************************************
# Input delay and output delay to each IO pins
### TX path output delay ###
set_output_delay -clock TX_CLK_OUT_125 -min -2.95 \
[get_ports "phy_rgmii_rgmii_txd* phy_rgmii_rgmii_tx_ctl"] -add_delay
set_output_delay -clock TX_CLK_OUT_125 -max -0.85 \
[get_ports "phy_rgmii_rgmii_txd* phy_rgmii_rgmii_tx_ctl"] -add_delay
set_output_delay -clock TX_CLK_OUT_125 -min -2.95 \
[get_ports "phy_rgmii_rgmii_txd* phy_rgmii_rgmii_tx_ctl"] -clock_fall -add_delay
set_output_delay -clock TX_CLK_OUT_125 -max -0.85 \
[get_ports "phy_rgmii_rgmii_txd* phy_rgmii_rgmii_tx_ctl"] -clock_fall -add_delay
#**************************************************************
# Multi-cycles & False paths
#**************************************************************
### to align the launch edge with the latch edge ###
set_multicycle_path 0 -setup -end -rise_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] -rise_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"]
set_multicycle_path 0 -setup -end -fall_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] -fall_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"]
### false path for different edge between lauch and latch clocks ###
set_false_path -fall_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] \
-rise_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"] -setup
set_false_path -rise_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] \
-fall_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"] -setup
set_false_path -fall_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] \
-fall_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"] -hold
set_false_path -rise_from [get_clocks "TX_SRC_CLK_125 TX_SRC_CLK_25 TX_SRC_CLK_2_5"] \
-rise_to [get_clocks "TX_CLK_OUT_125 TX_CLK_OUT_25 TX_CLK_OUT_2_5"] -hold
I believe the timing constraint is fine. The example used Quartus 14.0.2, but I used Quartus 18.1 to compile. Is the Quartus software cause this timing violation, how I can solve this problem?
By the way, I also tried the example in AN706, which route emac from hps to fpga but uses GMII interface instead. There is also timing violation from data clock (emac0_tx_clk) to output clock (enet1_tx_clk). Again, in AN706, the design was based on quartus prime standard version 14.0, but I use 18.1.
Does anybody know how to fix this, any reply is appreciated.
