Occasional Contributor
Super ContributorThanks, I see that your timing violation now are minimal. The slack now are quite low and some of the similar path are passing the timing but some of it not for hold and setup. I am using latest release Quartus 18.1.1 with all the upgrade done.
What you can do is:
1) overconstrain the design base on https://fpgawiki.intel.com/wiki/Timing_Constraints
2) change some of the pin location assignment, I would suggest you let it float if possible.
Thanks
Occasional ContributorHi,
Thank you very much for the quick response.
The setup violation for slow 1100 mV 0C Model is about -0.241 ns, is it what you get when you use the latest version 18.1.1?
When you say let the pin float, do you mean let rgmii pin float?
Thank you in advance!
Best regards
Jasmine
Occasional ContributorHi,
I removed pin assignment for gmii interfaces, the timing was not improved, I checked the pins were assigned by Quartus to a different locations.
I then assigned gmii interfaces to other locations, I got those timing violations:
Slow 1100 mV 85 C model
-0.024 ns setup
-0.014 ns hold
Slow 1100 mV 0 C model
-0.062 ns setup
-0.057 ns hold
Looks like the timing improved a little bit after I change the pin location manually.
Well, since there are setup timing violation for all the tx pins, and hold timing violation for part of tx pins, I do not know where the over constraint should be set. Because the same path (e.g. from clock_ena to tx_d) is too long for setup analysis, but short for hold analysis.
I'm trying seed sweep (20 seeds), I will update the result when it's done.
Best wishes
Jasmine
Occasional ContributorSeed sweep does not help at all, all 20 seeds failed.
