Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi,

It's hard to close the timing by adjust D5. Because there is both setup and hold timing violations. And the timing violation happens not only on one tx channel, but on almost all the tx channels.

See one of the path, in the attachment, the setup timing is fine, but hold timing fails.

The main problem I think is the path between CLKCTRL_G8 to *DDIO_outa[*]|muxsel.

As you can see, for setup timing, the delay on this path for data arrival path is 2.921, for data required path is 2.250, the difference is 0.671

for hold timing, the delay on this path for data arrival path is 2.244, for data required path is 2.929, the difference is 0.685.

The difference is too big.

Is there any way to reduce this difference?

With best wishes

Jasmine