Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Further check, the rgmii interface constrain that use for old version of Quartus might be incorrect. You will have to look for the constrain again with the latest release Q18.0. Our suggestion is look into the https://fpgacloud.intel.com/devstore/platform/?search=triple&acds_version=any&family=cyclone-10-lp for referrence. After you have modify the *sdc files, you can send again the design.qar if the timing still failed.