Forum Discussion

Occasional Contributor

6 years ago

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...

KennyT_altera

Super Contributor

6 years ago

I look into the design, whenever they are two different clock domain. Timing will be different.

Since the violation is not much on those path, what I suggest you try different seeds to see if it can close the timing. As the timing had been close in Q14.0 before. https://fpgawiki.intel.com/uploads/e/e6/FittingAlgorithms_and_SeedSweeps.pdf

Mingyuexin

Occasional Contributor

6 years ago

Thank you very much for the advice. It seems I have to do seed sweep manually, i.e. set different see value and see which one can close the timing. I have tried several seeds, I have not found any see which can close the timing yet.

Is there any trick to find the right seed faster? For example, do seed sweep automatically?

Forum Discussion

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

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