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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Thanks, I see that your timing violation now are minimal. The slack now are quite low and some of the similar path are passing the timing but some of it not for hold and setup. I am using latest release Quartus 18.1.1 with all the upgrade done.

What you can do is:

1) overconstrain the design base on https://fpgawiki.intel.com/wiki/Timing_Constraints

2) change some of the pin location assignment, I would suggest you let it float if possible.

Thanks

Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi,

Thank you very much for the quick response.

The setup violation for slow 1100 mV 0C Model is about -0.241 ns, is it what you get when you use the latest version 18.1.1?

When you say let the pin float, do you mean let rgmii pin float?

Thank you in advance!

Best regards

Jasmine