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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago
Hi Liu, Since your design download from rocket board, can you post the question there? The answer is yes, whenever there is a quartus change, routing and placement will change and you will have to close the timing again. If rocket board .com cannot help, you will have to attached your design.qar here for us to look into the failure.
Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi, Thank you very much for the reply.

I asked rocketboard, they did not reply at all.

Also I tried version 14.1, 15.0, all of them have timing violation.

My project is attached here, please help me with it. My project is compiled with quartus prime 18.1