Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi,

I removed pin assignment for gmii interfaces, the timing was not improved, I checked the pins were assigned by Quartus to a different locations.

I then assigned gmii interfaces to other locations, I got those timing violations:

Slow 1100 mV 85 C model

-0.024 ns setup

-0.014 ns hold

Slow 1100 mV 0 C model

-0.062 ns setup

-0.057 ns hold

Looks like the timing improved a little bit after I change the pin location manually.

Well, since there are setup timing violation for all the tx pins, and hold timing violation for part of tx pins, I do not know where the over constraint should be set. Because the same path (e.g. from clock_ena to tx_d) is too long for setup analysis, but short for hold analysis.

I'm trying seed sweep (20 seeds), I will update the result when it's done.

Best wishes

Jasmine