Forum Discussion
Mingyuexin
Occasional Contributor
Occasional ContributorTiming violation when route emac from HPS to FPGA in quartus prime standard 18.1
Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera
Super Contributor
Super ContributorFurther check, the rgmii interface constrain that use for old version of Quartus might be incorrect. You will have to look for the constrain again with the latest release Q18.0. Our suggestion is look into the https://fpgacloud.intel.com/devstore/platform/?search=triple&acds_version=any&family=cyclone-10-lp for referrence. After you have modify the *sdc files, you can send again the design.qar if the timing still failed.
MingyuexinHi,
I took this https://fpgacloud.intel.com/devstore/platform/?search=triple&acds_version=any&family=cyclone-10-lp for referrence, this time, not only setup time has violation, but also hold time.
See the attached project.
