Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

I see your report. This is a small delay happened from register to IO. Now u can try tune the d5 of d4 delay to close the remaining timing. D5 or d4 delay is shown in the IO, try to search it in the chip planner -> look into the specific IO -> resource property -> in the resource property editor -> right click on the triangle sign and see if you can modify the timing. Or you can just play around the value in the assignment editor.