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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

If you refer to the document above, you can use dse to do automatically seed. There are no magic seed for it. If you have try about 20seeds and it still failed timing, means we have to look for another way to close the timing.

  • Mingyuexin's avatar
    Mingyuexin
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Thank you very much again.

    Yes, I tried 13 seeds already, all of them fails the timing. The timing slack is about between -0.3 to 0.4 ns, I do not think seed selection can solve this problem, any other way we can use to solve this timing issue?

    Thank you in advance!