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khacker's avatar
khacker
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11 months ago
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Pin Delay information, Cyclone V SE, UBGA672

I am looking for any information about pin delay, pin/package lenghts, pin propagation delays of a Cyclone V SE FPGA, UBGA672, necessary for proper length matching of DDR3 design.
Thanks a lot.
best regards, Klaus

Board Debug

11 Replies

    • khacker's avatar
      khacker
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      11 months ago

      Hello. No, it's not a simulation. I want to create a PCB layout with exact length matching, especially for the DDR-bus.
      I need the pin/package lengths (i.e. the respective distance of a signal from the die to the ball) so that I can take these differences into account when matching from the solder pad onwards.
      Best regards, Klaus

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        11 months ago
        Yes but you should be performing a board simulation using the IBIS model to have an accurate guide of what lengths you should be using on your board to guarantee timing and signal integrity.
    • khacker's avatar
      khacker
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      11 months ago

      --> 5CSEBA2U23C8N

      What I actually need is the total pin lengths of all the signal pins of "5CSEBA2U23C8N" (Cycone V SE FPGA).
      Is this information part of an IBIS model?
      Could it got extracted from IBIS?

    • khacker's avatar
      khacker
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      11 months ago

      Hi.
      I've imported this IIBS model to the Symbol, but not one pin got a pin delay information from it.
      I also couldn't find any delay information within the *.ibs-files (search in a text reader).
      Only hint to some DiffPins --> NA (see screen shot)

       


      Maybe this parameter is not supported by this IBIS model?

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        11 months ago
        This is not how IBIS models are used. If you are planning on designing and building a custom board, you should know how to perform a board sim.
  • khacker's avatar
    khacker
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    11 months ago

    According to the Altium layout software description, it should be possible to get the pin-delay-information from an IBIS file.

    https://www.youtube.com/watch?v=E9CCjaTFCzs



    These delay values can be used and set for each pin of schematic symbols, and than can be considered in signal length matching within doing the pcb layout (especially for Data- and Address-Lanes of DDR3 routing).

    Other manufactures often provide the pin delay info in separate files or tables.

    But it seems the IBIS file for Cyclone V does not include any pin delay values; isn't it?

    • khacker's avatar
      khacker
      Icon for New Contributor rankNew Contributor
      11 months ago

      Hello,
      Thank you very much. I think that no further support will be necessary in this matter.

      Obviously neither the documentation nor the ibis model contains information about the individual pin delays.
      I am confident that our layout will work without taking these parameters into account, as this was not taken into account on any of the eval boards.


      Thanks again.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.