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New ContributorPin Delay information, Cyclone V SE, UBGA672
I am looking for any information about pin delay, pin/package lenghts, pin propagation delays of a Cyclone V SE FPGA, UBGA672, necessary for proper length matching of DDR3 design. Thanks a lot. be...
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
