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New ContributorAgilex 5 reconfigurable PLL - emif
Trying to reconfig a PLL with the EMIF Calibration IP
debug via system console
Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
enabled dynamic config within IOPLL and included EMIT Calib.
writing to divide setting addresses -> changes are immediate
multiple pure phase shifts did not work (work randomly)
is there a bit to start the shift
with one design setting N - M - C worked but no multiple shifts
with an other design problems writing to 0x80 to reset pll after setting NMC, no replay
for new nmc setting 6.4.1 enable | 6.4.2 clear calib | 6.4.3 reconfig | 6.4.4 recal
for just phase shifting 6.4.1 read modify write 6.4.3 without 0x80
2.2.12 perform positive or negative phase shift - is there a bit for that?
Where did I go wrong?
6 Replies
Farabi_AlteraRegular Contributor
Hello,
Section 2.2.12 explains the PLL phase shift feature.
Phase shift behavior may depend on:
1- PLL locked status
2- Recalibration is triggered or not
3- EMIF IP is actively using the PLL or not
Regarding 0x80 reset is not responding- 0x80 is used to reset the PLL, but you need to make sure the PLL is not in used by EMIF or other IPs, and need to make sure PLL is not in locked status.
Try to follow below sequence :
1- Enable Reconfig
2- Clear calibration
3- Write new settings
4- Trigger Recalibration
regards,
Farabi
SamoThanks a lot for your reply,
with your sequence i can shift from 0 to 7 times t_shift (= T_vco/8 ).
So i can shift 0 or 1 or 2 or .. 7 times t_shift
My problem is I like to shift for example 20 times t_shift
Repeating your sequence with 4 times 5 t_shifts does only shift once
For example only one time 5 t_shift
If i dont do "4-Trigger Recalib" but insert after each shift a 0-shift
then it shifts more than the 0..7 range but not continuously (sometimes even changing direction)
1- enab reconfig
2- clear calib
loop
3a- write phase shift nr>0 (1..7)
3b- write phase shift nr=0 (0)
Is this the sequence for multiple shifts?
And how to perform positive or negativ shift 2.2.12 is there a bit for the direction?
LenzHydHello Sir or Madam,
I have a similar problem. I am able to perform multiple phase shifts (more than seven), but some of them do not work properly.
To be more precise, most shifts behave as expected (roughly four out of five, although this is not entirely consistent), but occasionally the clock signal is shifted by much more than the intended 100 ps.I would like to build a tapped delay line, and inconsistent phase shifts make this difficult.
I look forward to your reply.
Kind regards,
Lenz- AqidAyman_Altera
Hi Lorenz,
For your issue, are you using the HSIO or HVIO I/O PLL block type?
Thanks.
- LenzHyd
Hi,
we are using the calbus and EMIF calibration IP to reconfigure the PLL. Thus according to the Agilex 5 Clocking and PLL user guide, this shoud result in a HSIO I/O PLL block type.
Thank you for your help.
Kind regards,
Lenz
