Forum Discussion
New ContributorPin Delay information, Cyclone V SE, UBGA672
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
Super ContributorYou probably want the IBIS model so you can perform a board simulation: https://www.intel.com/content/www/us/en/content-details/674909/cyclone-v-ibis-models-zip.html?wapkw=cyclone%20v%20ibis%20models
khackerHello. No, it's not a simulation. I want to create a PCB layout with exact length matching, especially for the DDR-bus.
I need the pin/package lengths (i.e. the respective distance of a signal from the die to the ball) so that I can take these differences into account when matching from the solder pad onwards.
Best regards, Klaus- sstrellYes but you should be performing a board simulation using the IBIS model to have an accurate guide of what lengths you should be using on your board to guarantee timing and signal integrity.
- khacker
--> 5CSEBA2U23C8N
What I actually need is the total pin lengths of all the signal pins of "5CSEBA2U23C8N" (Cycone V SE FPGA).
Is this information part of an IBIS model?
Could it got extracted from IBIS? - khacker
Hi.
I've imported this IIBS model to the Symbol, but not one pin got a pin delay information from it.
I also couldn't find any delay information within the *.ibs-files (search in a text reader).
Only hint to some DiffPins --> NA (see screen shot)
Maybe this parameter is not supported by this IBIS model?- sstrellThis is not how IBIS models are used. If you are planning on designing and building a custom board, you should know how to perform a board sim.
