Forum Discussion
New ContributorPin Delay information, Cyclone V SE, UBGA672
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
Super ContributorYou probably want the IBIS model so you can perform a board simulation: https://www.intel.com/content/www/us/en/content-details/674909/cyclone-v-ibis-models-zip.html?wapkw=cyclone%20v%20ibis%20models
New Contributor--> 5CSEBA2U23C8N
What I actually need is the total pin lengths of all the signal pins of "5CSEBA2U23C8N" (Cycone V SE FPGA).
Is this information part of an IBIS model?
Could it got extracted from IBIS?
