Forum Discussion
New ContributorPin Delay information, Cyclone V SE, UBGA672
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
New ContributorAccording to the Altium layout software description, it should be possible to get the pin-delay-information from an IBIS file.
https://www.youtube.com/watch?v=E9CCjaTFCzs
These delay values can be used and set for each pin of schematic symbols, and than can be considered in signal length matching within doing the pcb layout (especially for Data- and Address-Lanes of DDR3 routing).
Other manufactures often provide the pin delay info in separate files or tables.
But it seems the IBIS file for Cyclone V does not include any pin delay values; isn't it?
