Forum Discussion
New ContributorPin Delay information, Cyclone V SE, UBGA672
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
Regular ContributorThank you @sstrell for the input provided.
May I know if you need more information/support on this request?
New ContributorHello,
Thank you very much. I think that no further support will be necessary in this matter.
Obviously neither the documentation nor the ibis model contains information about the individual pin delays.
I am confident that our layout will work without taking these parameters into account, as this was not taken into account on any of the eval boards.
Thanks again.
