sstrellSuper ContributorJoined 7 years ago3691 Posts364 LikesLikes received289 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Not received badge verilog hdl basics after completion . The email is mailto:[email protected] now and I think you only get a badge if you attend an Altera-taught instructor-led class. Re: Is there any way to script the creation of a signal tap instance? The latter: put Signal Tap in a reusable design block and make multiple design blocks that you can basically just swap in and out. As mentioned, you can't set up the .stp file without using the GUI. Re: Is there any way to script the creation of a signal tap instance? You may want to look at a block-based design approach, creating reusable design partitions that include Signal Tap instances. There's a user guide all about doing this in Pro: https://docs.altera.com/r/docs/683247/current Re: I want to understand the practical difference between Best Speed and Smallest Area in FPGA . I'm not sure what "the image would occasionally and intermittently split" means as the issue, but is your design meeting timing? How fast are you running it? Like it says there, best speed is inserting an additional register. Are you taking into account this extra cycle of latency elsewhere in your design? Re: Generate License by Activation Code Not Working Where did you purchase the license? Have you checked with them? You have to be logged in to the SSLC with the correct account for a particular code. If for some reason the vendor didn't use the correct email address, this might happen. Re: adding signal to debug/signaltap You add signals using the graphical .stp file. Just double-click in the Node List to open the Node Finder and add signals. If you are talking about post-fit signals, there is a "Preserve for debug" assignment in the Assignment Editor that marks signals so they are not optimized away during compilation. As for adding signals from a command line? I don't see options for it: https://docs.altera.com/r/docs/683819/26.1/quartus-prime-pro-edition-user-guide/signal-tap-command-line-options Re: SDM Monitoring & Thermal Behavior Better to use the PTA now instead: https://docs.altera.com/r/docs/865226/current Re: How to create a Packaged Subsystem in TCL The script from the GUI is assuming the packaged subsystem has already been created. Running it standalone, you can't set_package_property unless you've created a package first. I don't see offhand the Tcl command for doing this, but you can check the Platform Designer messages window when you open the dialog box to see the equivalent command to add to your script. Your script also probably has to call an executable to load the Tcl package that contains set_package_property. I've never scripted this so I'm not sure what's needed, but hopefully this gives you enough to figure it out. Re: Unable to checkout a viewer license Agreed. Just get a fixed node no cost license for Quartus and Questa from the SSLC. Re: SSLC Login Issue – "You need to enroll" loop after OTP verification Go to your dashboard after signing in to MyAltera at https://www.altera.com/myaltera Do you see the SSLC listed there in the main boxes of your dashboard? If not, go to https://www.altera.com/SSLC and click Register. For some reason, it's an additional registration on top of MyAltera.