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sstrell
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Re: Quartus® Prime 90-Day Evaluation License + IPs
Those IPs are both labeled as supporting OpenCore Plus (I think now it's just called IP Evaluation Mode), so you can design with them, simulate them, and even generate a programming file with them. However, you'll need to stay tethered to your device once you program the board until you purchase a license. Details here: https://docs.altera.com/r/docs/813669/26.1.1/triple-speed-ethernet-ip-user-guide-agilex-3-and-agilex-5-fpgas-and-socs/ip-evaluation-mode48Views0likes2CommentsRe: Unable to generate Agilex 5 bitstream with Quartus Prime Pro 25.1.0.129
Device support is added progressively in newer versions of Quartus starting with advanced models for simulation and design and progressing later to being able to generate a bitstream. You probably are going to need to upgrade your Quartus version to at least 25.1.1 to get a bitstream. Note that there is also now 25.3 and 26.1 versions as well.31Views0likes3CommentsRe: Schematics/layout for TerasIC SoCKit rev. D with Cyclone V
Assuming you're talking about this kit: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=183&No=816&PartNo=4#heading I don't have a direct answer, but it's highly unusual from my experience that Terasic does not include schematics. Have you tried contacting them or checked one of the older board rev downloads?35Views0likes0CommentsRe: quartus ii sub app windows download is too slow.
I'm not sure what a "sub app" is. And you most likely should be downloading Quartus Prime, not Quartus II, which hasn't existed for like a decade at this point. What exactly are you trying to download that you feel is too slow?58Views0likes1CommentRe: How to organize a shared cache for qsys systems?
_hw.tcl files, when created for new custom components via Component Editor, get placed in the Quartus project directory for some reason. Back in the day, they used to get placed along with the location of the HDL code that defined the custom component, making it easier to have that connection between _hw.tcl and the code. As for the connections between files, simply open the _hw.tcl file and you'll see the paths pointing to the associated code. Remember that .ip files define an instance of a component with a particular selection of parameter settings added to the system so it should point to the _hw.tcl, I believe. I can't help with the prior question.47Views0likes0CommentsRe: Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B
To do this, the EMIF I/O sub-banks must be "adjacent" to each other. Yes I/O banks 3A and 3B are physically adjacent to each other, but the I/O sub-banks must be adjacent for this to work and that means the "top" sub-bank (closest to the device edge) in 3A is adjacent to the "bottom" sub-bank (away from the device edge) in 3B, so you have to use these two particular sub-banks. Easiest way to make sure you set this up correctly is to use Interface Planner. I think the HPS PLL reference clock setup is unique. For standalone EMIF, you have to place in the appropriate sub-banks as I just mentioned to share the clock or drive the clock in to each interface separately from elsewhere.53Views1like0CommentsRe: Timing models don't match measured delays
How are you gathering the numbers in the table from the TA? Are you using data arrival times from whatever is driving these registers and from these registers to the output pins? I guess it's not clear what design you are using and what is actually driving these registers. Also not clear is your clocking setup. Are you using a PLL that's driving a global clock resource or are you driving the registers directly? I think more detail on your setup and how you are getting these numbers is needed.36Views0likes1Comment