sstrell
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Re: TimeQuest Question Relating PLL
Something is failing timing in the input clock domain, not the clock itself. You need to generate timing reports and understand what is failing timing. You should also generate an unconstrained paths report to make sure your design is considered fully constrained for timing. You might want to check the user guide (https://www.intel.com/content/www/us/en/docs/programmable/683243/25-3/faq.html) and training (https://learn.altera.com/learn/learning-plans/17/timing-analysis-with-the-alterar-quartusr-prime-pro-software) if you're not familiar with how to perform timing analysis and closure. You could also try posting your .sdc file here.14Views0likes0CommentsRe: Quartus/Signaltap complains about wrong version
.stp files aren't version-specific. No "upgrade" is necessary. But if you compiled the design in 24.2 and then recompiled in 24.1, that might change the logic analyzer enough so it doesn't work with the same .stp file. If not, then I stand by that the .stp file might be corrupted.2Views0likes0CommentsRe: Agilex 5 A5EC065BB32AE5SR0 issue
Are you trying to see this on a flashing LED or are you using a scope? You're not going to be able to see a multi MHz clock flash on an LED. What frequency is nios_clk? Have you made sure that the pin you assigned SYS_LED[0] in the Pin Planner is configured correctly (maybe needs a pull-up?)?28Views0likes0CommentsRe: Shift Register triggers occassionally on both clock edges
Signal names on the Signal Tap capture would be helpful. Is your design meeting timing? The code could also use some clean up, combining the if blocks for the counter operation and performing the shift. And as mentioned, what are you using as the acquisition clock in Signal Tap?19Views0likes3CommentsRe: Clock Domains and Clock Domain Crossing (CDC)
The whole point here is to guide the Fitter after cutting timing between the two clock domains, so the answer to your first question is yes. The two domains are cut from each other and then set_max_skew and set_data_delay are used to define skew between bus paths between the clock domains and the data path delay between the endpoints of the two sides of the cut paths. As for the values to use, just use the recommended values you show in that slide.19Views0likes0CommentsRe: DK-DEV-AGI027RES Install Package
Do you mean from here?: https://www.altera.com/products/devkit/a1jui0000049utmmam/agilex-7-fpga-i-series-development-kit-2x-r-tile-and-1x-f-tile ES is engineering sample but usually you can use the final installers for ES boards unless noted.33Views0likes3Comments