Forum Discussion
New ContributorPin Delay information, Cyclone V SE, UBGA672
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
Super ContributorYou probably want the IBIS model so you can perform a board simulation: https://www.intel.com/content/www/us/en/content-details/674909/cyclone-v-ibis-models-zip.html?wapkw=cyclone%20v%20ibis%20models
New ContributorHello. No, it's not a simulation. I want to create a PCB layout with exact length matching, especially for the DDR-bus.
I need the pin/package lengths (i.e. the respective distance of a signal from the die to the ball) so that I can take these differences into account when matching from the solder pad onwards.
Best regards, Klaus
- sstrellYes but you should be performing a board simulation using the IBIS model to have an accurate guide of what lengths you should be using on your board to guarantee timing and signal integrity.
