Forum Discussion
khacker
New Contributor
New ContributorPin Delay information, Cyclone V SE, UBGA672
I am looking for any information about pin delay, pin/package lenghts, pin propagation delays of a Cyclone V SE FPGA, UBGA672, necessary for proper length matching of DDR3 design. Thanks a lot. be...
If the device handbook does not include this information or the IBIS file, it may be because FPGAs are completely customizable and the delay may be different depending on the design. You probably want to go through the EMIF documentation here to know what you need to do: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/ddr2-and-ddr3-sdram-board-design-guidelines.html
khackerNew Contributor
New ContributorHi.
I've imported this IIBS model to the Symbol, but not one pin got a pin delay information from it.
I also couldn't find any delay information within the *.ibs-files (search in a text reader).
Only hint to some DiffPins --> NA (see screen shot)
Maybe this parameter is not supported by this IBIS model?
sstrell
Super Contributor
Super ContributorThis is not how IBIS models are used. If you are planning on designing and building a custom board, you should know how to perform a board sim.
