50 Results
Critical Warning(24567): The design is using an internal oscillator along with transceivers, EMIF, MIPI, and PHY Lite interfaces.
...esign contains Transceiver IP, External Memory Interface (EMIF) IP, Mobile Industry Processor Interface (MIPI) D-PHY IP or PHY Lite for Parallel Interfaces FPGA IP and you have the following options e...57Views0likes0CommentsWhy can the PLL not be instantiated when using PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, the phase-locked loop (PLL) cannot be instantiated on the top sub-bank when using PHY Lite for P...80Views0likes0CommentsWhy are there intermittent bit errors on the PHY Lite for Parallel Interfaces IP for Agilex™ 7 FPGA and Agilex™ 9 FPGA input path designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 21.4, you might find functional failures or bit errors on Periphery-to-Core- Core (P2C) paths when using the PHY Lite...quartus-21.4-0.02-readme.txt104Views0likes0CommentsWhy does compiling the PHY Lite for Parallel Interfaces IP example design for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate invalid Fitter assignment warnings?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that the PHY Lite for Parallel Interfaces IP example design compilations for Agilex™ 3 FPGA C...79Views0likes0CommentsWhat are the supported simulators for PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP?
Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 22.4, the supported simulators with PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP are limited to VCS*, V...56Views0likes0CommentsWhy the RTL simulation is failing with PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, you might see the errors below when simulating the PHY Lite for Parallel Interfaces Intel Agilex® 7...59Views0likes0CommentsIs bit 12 of the Strobe Enable Phase register in the PHY Lite for Parallel Interfaces IP for Agilex™ 7 FPGA F-Series and I-Series devices the enable bit to select between the Control Status R...
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might see that bit 12 of the Strobe Enable Phase register in the PHY Lite for Parallel I...80Views0likes0CommentsHow do I enable the Avalon override in RTL simulation for PHY Lite for Parallel Interfaces Intel® Agilex™ 7 FPGA IP ?
...valon* override. In the PHYlite example design with Dynamic Reconfiguration, this step is performed as the IOSSM_INIT_WRITE state in the test_logic_iossm module of the tester IP. Additional I...26Views0likes0CommentsWhy does the PHY Lite for Parallel Interfaces IP Parameter Editor GUI not produce any error message when input or bidirectional pins are placed in the same lane as RZQ using POD I/O standards?
Description Due to a problem in Quartus® Prime Pro Edition Software version 24.3, you might see that the PHY Lite for Parallel Interfaces IP Parameter Editor GUI does not produce an error m...66Views0likes0CommentsWhy is the clock frequency of *usr_clk different when multiple instances of PHY Lite for Parallel Interfaces FPGA IP are implemented
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the clock frequency of *usr_clk when multiple instances of the PHY Lite for Parallel I...34Views0likes0Comments