Critical Warning(24567): The design is using an internal oscillator along with transceivers, EMIF, MIPI, and PHY Lite interfaces.

Description

Starting from the Quartus® Prime Pro Edition Software version 24.3, you may see this Critical Warning if your Stratix® 10 FPGA,  Agilex™ 7 FPGA  or Agilex™ 5  FPGA design contains Transceiver IP, External Memory Interface (EMIF) IP, Mobile Industry Processor Interface (MIPI) D-PHY IP or PHY Lite for Parallel Interfaces FPGA IP and you have the following options enabled : 

set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_<25/100/125>MHZ
set_global_assignment -name RUN_CONFIG_CPU_FROM_INT_OSC ON

Resolution

You must ensure that you always supply a free-running clock at the specified frequency on the OSC_CLK_1 pin during configuration and user mode if your design contains any of the aforementioned IP. 
Provided you do this, this critical warning can be ignored.

This Critical Warning will be removed in a future version of Quartus® Prime Pro Edition software when both aforementioned assignments are in the design.