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Petkov_Alex's avatar
Petkov_Alex
Icon for Occasional Contributor rankOccasional Contributor
1 day ago

S10 hps fpga2sdram bridge low speed

Hello, i have some problems 

I have a project with stratix 10 with hps

I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width

Via u-boot smc configured and enabled them, but measured speed is not enough.

When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz)

But when I use all 3 bridges it becomes 20 gbit/s

I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge 

ECC in emif (hmc) is disabled

I tried to use QoS for bridges, set them to bypass

P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps)

Quartus Pro 21.4

Any help would be useful!

general
Hps Arch
Hps Debug

2 Replies

  • Qingrui_H_Intel's avatar
    Qingrui_H_Intel
    Icon for New Contributor rankNew Contributor
    7 hours ago

    Hi Alex,

    When you use all 3 bridges, it becomes 20 gbit/s for each interface or 20 gbit/s for all the 3 interfaces? And does each axi fpga2sdram bridge be connected to its own avmm interface? And how is the address pattern on each interface? Sequential write or random write?

    • Petkov_Alex's avatar
      Petkov_Alex
      Icon for Occasional Contributor rankOccasional Contributor
      7 hours ago

      Thanks for your questions.

      When I use 3 bridge whole throughput becomes 20 gbit/s, its sum of 3 bridges.

      And each bridge have own avmm interface.

      I use constant different address for each bridge, and burst 128 write with 128 bit data, for examle 0x20100000, 0x20200000, 0x20300000

      So it has sequential writes