S10 hps fpga2sdram bridge low speed

Hi Petkov_Alex​ ,

May I know whether you have any updates on this issue or is it been resolved already?

Thanks

Regards

Kian

Hi Petkov_Alex​ 
Apologies for the slow delay in responding back to your issue. I was looking at this case and just wondering on some of your description on the issue

• Wready is often 0, it means, that slave (axi in this case) is not ready to receive data. Awready is almost times 1.

AWREADY is always high meaning HPS interconnect (or the cache coherency unit) is accepting your write address (queue is empty and waiting for next one)

WREADY is often low/0, means the actual data FIFO in HPS is full, meaning it cannot push the actual data to SDRAM fast enough to cater for the incoming writes,  creating some backpressure/bottleneck in the system

I saw there is a KDB on Stratix 10 low memory write but this is on HBM side which supposedly fixed in Quartus 22.2 

What could be the reason for the low write performance Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP write response path in AXI backpressure mode? | Altera Community - 347633

I will try see any other documentation to see anything related to this case.

• I use constant different address for each bridge, and burst 128 write with 128 bit data, for example 0x20100000, 0x20200000, 0x20300000

So if I understand correctly, it translates into 128 writes * 16bytes = 2048 bytes  

Initially i thought might be the 4KB boundary limit but your transaction is within there so no issues as long as its within the boundary.

0x20100000 (bridge 1) , 0x20200000 (bridge 2), 0x20300000 (bridge 3) = gap 1048 bytes (1MB) . Could it be accessing the same bank but different row in parallel thus causing the DDR row thrashing? Just assumption here , possible for you to test spacing the test addresses by 256 MB (e.g., 0x10000000, 0x20000000, 0x30000000) to ensure they naturally hit different banks or bank groups

Thanks

Regards

Kian

Maybe some ideas or I already got max available throughput speed? If yes, I think it's better to change speed characteristics in documentation or describe limitations.

Hi Alex,

When you use all 3 bridges, it becomes 20 gbit/s for each interface or 20 gbit/s for all the 3 interfaces? And does each axi fpga2sdram bridge be connected to its own avmm interface? And how is the address pattern on each interface? Sequential write or random write?