Forum Discussion
Petkov_Alex
Occasional Contributor
Occasional ContributorS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them,...
Qingrui_H_Intel
New Contributor
New ContributorHi Alex,
When you use all 3 bridges, it becomes 20 gbit/s for each interface or 20 gbit/s for all the 3 interfaces? And does each axi fpga2sdram bridge be connected to its own avmm interface? And how is the address pattern on each interface? Sequential write or random write?
Petkov_AlexOccasional Contributor
Occasional ContributorAs described in doc (AN 802, page 38) each bridge with 128 bit width and 400 mhz frequency have 6,4 GB/s(51,2 Gb/s)
And of course, it's ideal, so i expect 80% of it
