Occasional Contributor
New ContributorHi Alex,
When you use all 3 bridges, it becomes 20 gbit/s for each interface or 20 gbit/s for all the 3 interfaces? And does each axi fpga2sdram bridge be connected to its own avmm interface? And how is the address pattern on each interface? Sequential write or random write?
Occasional ContributorThanks for your questions.
When I use 3 bridge whole throughput becomes 20 gbit/s, its sum of 3 bridges.
And each bridge have own avmm interface.
I use constant different address for each bridge, and burst 128 write with 128 bit data, for examle 0x20100000, 0x20200000, 0x20300000
So it has sequential writes
New ContributorPlease try to change the "Address Ordering" in EMIF ip to see the other 2 settings can help improve this. And you can also monitor the transactions on AXI F2SDRAM interface to see the real write commands in these interface to ensure if the burst commands in avmm is split or not.
Occasional ContributorUnfortunately, test results are the same. AXI signal len (as burst in avalon mm) is as burst.
Wready is often 0, it means, that slave (axi in this case) is not ready to receive data. Awready is almost times 1.
Maybe its bug or unexpected behaviour?
Or I have to write some "magic" register via u-boot?
And am I right, that expect more than 20 gbit/s via 3 bridges?
May there is some example design for dev kit, that achieves speed, described in documentation?
Occasional ContributorAs described in doc (AN 802, page 38) each bridge with 128 bit width and 400 mhz frequency have 6,4 GB/s(51,2 Gb/s)
And of course, it's ideal, so i expect 80% of it
