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zamroodh's avatar
zamroodh
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4 months ago

Agilex 5/3 FreeRTOS SMP Support

Stable Version: v25.4
Quartus Version: 25.4
Supported devices: Agilex™ 3 and Agilex™ 5
Source : https://github.com/Ignitarium-Technology/freertos-socfpga
Branch/Tag: v25.4-SMP
Release Date: March 30, 2026

Hello Everyone,
FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started.

Features and comments

FeaturesAgilex3Agilex5Agilex3 SMP

Agilex5 SMP
(A55 x 2 or A76 x 2)

Supported featuresLimitations/ Known issues
A55 bootYesYesYesYes

Single core boot, Dual core SMP

 
A76 bootNAYesNAYes

Single core boot, Dual core SMP

 
QSPI bootYesYesYesYes  
SD bootYesYesYesYes  
eMMC bootYesYesYesYes  
NAND bootNoNoNoNo  
Clk mngr driverYesYesYesYes

API to get clock speed of different blocks

 
Reset mngr driverYesYesYesYes

Peripheral reset assert/de-assert

 
DMA driverYesYesYesYes

Memory to memory transfer

Only support memory to memory

GPIO driverYesYesYesYes

Write, read and interrupt support

 
Timer driverYesYesYesYes

User defined and free running modes

 
UART driverYesYesYesYes

Full duplex Tx and Rx

DMA not supported (Planned for future release

I2C driverYesYesYesYes

Master mode write and read Standard and fast modes

DMA not supported (Planned for future release

I3C driverYesYesYesYes

Master mode write and read i3c and legacy i2c devices

IBI not supported (Planned for future release)

SPI driverYesYesYesYes

Master mode write and read

DMA is not supported

QSPI driverYesYesYesYes

QSPI flash read/write/erase

 
NAND driverNoNoNoNo  
SDM mailbox driverYesYesYesYes

SDM commands with SIP_SVC

 
SMMU enable supportYesYesYesYes

Static identity mapping for cache coherency

 
SDMMC driverYesYesYesYes

standard and HS speeds SDMMC and eMMC devices
Fat FS support

 
Ethernet stackYesYesYesYes

TCP/IP, UDP, ICMP and DHCP
IPv4 and IPv6 support

 
USB 2.0 stackNTYesNTYes

USB mass storage class

 Tested with a custom board and SOF
USB 3.1 stackNTYesNTYes

USB mass storage operation

 
WDT diverYesYesYesYes

interrupt or reset on timer expiry

 
EDAC supportYesYesYesYes

Error injection and detection for EMAC, USB and QSPI blocks

OCRAM not supported

IOSSM driverYesYesYesYes

Error injection and detection

 
Bridge driverNTYesNTYes

Enable, Disable

 
Reboot mngrYesYesYesYes

Warm/Cold reboot

 
FPGA managerYesYesYesYes

FPGA configuration

 

Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested

Note: If you find any issues, please raise an issue in the GitHub page.
For more support/assistance visit our website .

Arm Processor
embedded peripheral
Hps Boot
operating system
Sw Development

9 Replies

  • sonycman's avatar
    sonycman
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    1 day ago

    I thought i see now.

    core.rbf file was stripped of bootloader code before being written to sd card.

    And QSPI contains .sof data too to support both HPS-first and FPGA-first boot modes, am i right?

     

    In FPGA-first bitstream being loaded from QSPI, and in HPS-first bitstream being taken from sd card core.rbf?

    • kevinsuresh's avatar
      kevinsuresh
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      11 hours ago

      Hi sonycman,

      The qspi_image.jic contains the properties of the .sof file we used to build the application. The sof file decides where the HPS or FPGA gets configured first. So it can't support both modes at once.

      In FPGA first boot, the bitstream gets configured at boot automatically. For the HPS first boot, the FPGA doesn't get configured until we use the fpga_manager driver to configure the FPGA. To make this easier, the sd_img contains the core.rbf bitstream file required for FPGA configuration so that the user doesn't need to build it and copy it.

      Hope this helps

      • sonycman's avatar
        sonycman
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        11 hours ago

        Hi kevinsuresh,

        Thank you, now i get it. There is much to learn for me :)

        It seems bl31 secure monitor could not be excluded entirely? Its services heavily used?

  • sonycman's avatar
    sonycman
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    1 day ago

    Hi Naji_Naufel,

    Yes, its the same page you are linked above, SD boot paragraph.

    As well as i understand, qspi_image.jic contains BL2 bootloader and .sof FPGA bitstream.

    The same is core.rbf.

    So this command:  

    make_sdimage.sh -s 128 -o sd.img -p "a2:2:64:fip.bin" -p "c:1::fatfs/core.rbf"

    places on SD card the same files (in core.rbf) as in qspi image?

    As i understand, booting proceeds loading .sof and BL2 from QSPI first, then BL2 loads .fip from sd card fat partition.

    I'am interested for what the core.rbf (with doubled bl2 and .sof) was placed on sd card?

     

  • sonycman's avatar
    sonycman
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    1 day ago

    May i ask a question?

    Readme documentation Building boot images for SD card guides to make two files, sd_img and qspi_img.jic.

    And according to guide sd_img should contain .sof and bl2.hex files, which is wrong, if i'am understand correctly.

    Those two files must be in .jic, which is programmed to QSPI.

    SD card image should contain a fip image with user application and bl31 secure monitor.

    Am i wrong?